The invention is directed to an improved approach for implementing and visualizing die designs.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
The EDA tools may also be used to perform early stage analysis and examinations of an electronic design. For example, the process of performing chip planning can be greatly facilitated if the designer or chip planning tool can predict the expected die size and configuration for the IC product. However, the die size and configuration of the IC product is significantly affected by the configuration of the I/O ring and cores needed to support the IC product. The I/O ring is a top-level component within which all I/O related logic is instantiated, and is usually positioned around the periphery of the IC chip. Typical components on the I/O ring include, for example, I/O cells, power and ground cells, boundary scan registers (BSRs), pin structures, and/or other glue-logic structures. The IC core typically resides within the boundaries of the I/O ring, with the core typically including the internal blocks and connectivity of the IC chip.
For planning purposes, it is very desirable for engineers and architects to be able to obtain and visually review accurate estimates of the I/O ring and IC core configuration for the final IC product. One reason this functionality is useful is because this type of visualization and estimation allows the engineer or architect to know the required die size for the product. For example, consider that the I/O ring creates the peripheral boundary of the IC chip, which means that the amount of space available for the IC core is greatly affected by the size of the I/O ring. Therefore, the size and dimensions of the die are also greatly affected by the required dimensions of the I/O ring and the IC core structures. The size of the die for the IC product must be large enough to hold the required I/O ring structures as well as the core structures. Clearly, the most efficient die size is the situation when the dimensions of the minimum I/O ring periphery creates enough interior space to exactly match the required space of the core. If the total size of the periphery for the I/O ring is greater than what is needed to implement the core, the design is said to be “I/O limited”. A design is “core limited” if the core requires more space than the minimum periphery required to implement the I/O ring.
For a given electronic design, there may be any number of possible configurations that may be implemented for the die arrangement. The problem is that the designer often is not able to effectively visualize those different die arrangements along with their dimensional specifications, and hence is often not able to identify the most optimal die arrangement from among the different die arrangement options.